Arty A7 MicroBlaze DDR3 tutorial

Hi Viktor,

Thanks for posting this guide, it looks really clean and you've clearly put in a lot of work. So far I've followed as far as generating a bitstream, with a couple of minor deviations, in that I specified no buffer in the clocking wizard and did not use the real-time preset. It seems to have built great (other than a hiccup where I initially capitalized the name of the CLK100MHZ port wrong, simple user error) and I'll be testing the project further. The same steps and design should be applicable to any Digilent board with a 100 MHz system clock and a DDR interface, including Nexys A7, Arty S7, Nexys Video, USB104 A7. Some comments and a couple of questions follow:

2. We can't connect the external system clock to MIG directly

It is possible to connect the external clock to the MIG, but still requires manually creating the clock port and adding a constraint like you do for聽CLK100MHZ in order to override the 2.5 V logic standard that the MIG tries to set. That said, it looks like your approach is better than wiring the clock port directly to sys_clk_i, for reasons described below.

In fact, the A7-35 .xdc on GitHub seems to be wrong to me. It differs in the names of pins ck_io20..25, which are printed as ck_a6..11 on my specimen of A7-35. Do use A7-100 .xdc.

I've updated the 35T's template constraints on GitHub to use the correct naming convention.

Connect ck_rst to MIG.ck_rst

This should be the MIG's sys_rst port.

Do you set the clocking wizard input clock source to No Buffer? I might be missing where this happens in the guide. Not positive if the setting is ignored in this case, but warnings or errors can crop up on Zynq devices if a clocking wizard is fed by an fclk pin and the input source is left as a single-ended clock-capable pin.

Which version of the Arty A7 board files did you work with? I imagine that either 1.1 or 1.2 will be fine with the guide since you change the MIG configuration. On the off chance that someone uses v1.1, they will need to manually set the clock period to 3077 ps on the "Options for Controller 0 - DDR3 SDRAM" page of the MIG configuration.

It's also notable that having a clocking wizard fed from a "clean" 100 MHz signal should make it easier to generate a 25 MHz clock for the Ethernet reference clock when attempting to follow the Microblaze servers guide. The approach recommended by this guide,聽https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi,聽a "loopback" configuration where the PLL inside of the MIG is used to generate the reference clock, isn't quite able to do this the same way - the frequencies for the clocks output from the MIG are calculated based on the 3077 ps period, rather than on the 325 MHz frequency. This leads to weird rounding errors in how the clock frequencies are displayed in the block design, and can make it look like a 25 MHz clock generated off of the "324.99 MHz" clock is out of spec for the Ethernet PHY, at something around 24.8 MHz. It's more complex than what I've just described, since some displayed frequencies are derived from periods and some periods are derived from frequencies, and the MIG wizard doesn't seem to tell you what the underlying representation is. Post-implementation clock reports will show that the frequencies are actually okay, but the UI is misleading until you've nearly finished generating a bitstream. This is all to say that your implementation looks great since it lets you divide more clocks that show their frequencies correctly off of the 100 MHz system clock.

For reference, this is what the alternate approach looks like after the MIG clocks are wired up (image comes from the baremetal software guide, linked above):

聽

Do you mind if we link to your guide from the reference site to help point others in the right direction?

Thanks!

Arthur